Register map for the FDC1004Q component. More...

Macros
#define	FDC_CAPDAC_FACTOR 3.125
	CAPDAC multiplying factor.

#define	FDC1004Q_MEAS1_MSB 0x00
	MSB Portion of Measurement 1 Register. More...

#define	FDC1004Q_MEAS1_LSB 0x01
	LSB Portion of Measurement 1 Register. More...

#define	FDC1004Q_MEAS2_MSB 0x02
	MSB Portion of Measurement 2 Register. More...

#define	FDC1004Q_MEAS2_LSB 0x03
	LSB Portion of Measurement 2 Register. More...

#define	FDC1004Q_MEAS3_MSB 0x04
	MSB Portion of Measurement 3 Register. More...

#define	FDC1004Q_MEAS3_LSB 0x05
	LSB Portion of Measurement 3 Register. More...

#define	FDC1004Q_MEAS4_MSB 0x06
	MSB Portion of Measurement 4 Register. More...

#define	FDC1004Q_MEAS4_LSB 0x07
	LSB Portion of Measurement 4 Register. More...

#define	FDC1004Q_CONF_MEAS1 0x08
	Measurement 1 Configuration Register. More...

#define	FDC1004Q_CONF_MEAS2 0x09
	Measurement 2 Configuration Register. More...

#define	FDC1004Q_CONF_MEAS3 0x0A
	Measurement 3 Configuration Register. More...

#define	FDC1004Q_CONF_MEAS4 0x0B
	Measurement 4 Configuration Register. More...

#define	FDC1004Q_FDC_CONF 0x0C
	Capacitance to Digital Configuration Register. More...

#define	FDC1004Q_OFFSET_CAL_CIN1 0x0D
	CIN1 Offset Calibration Register. More...

#define	FDC1004Q_OFFSET_CAL_CIN2 0x0E
	CIN2 Offset Calibration Register. More...

#define	FDC1004Q_OFFSET_CAL_CIN3 0x0F
	CIN3 Offset Calibration Register. More...

#define	FDC1004Q_OFFSET_CAL_CIN4 0x10
	CIN4 Offset Calibration Register. More...

#define	FDC1004Q_GAIN_CAL_CIN1 0x11
	CIN1 Gain Calibration Register. More...

#define	FDC1004Q_GAIN_CAL_CIN2 0x12
	CIN2 Gain Calibration Register. More...

#define	FDC1004Q_GAIN_CAL_CIN3 0x13
	CIN3 Gain Calibration Register. More...

#define	FDC1004Q_GAIN_CAL_CIN4 0x14
	CIN4 Gain Calibration Register. More...

#define	FDC1004Q_MANUFACTURER_ID 0xFE
	ID of Texas Instruments Register. More...

#define	FDC1004Q_DEVICE_ID 0xFF
	ID of FDC1004Q device Register. More...

#define	FDC_OK 0
	No error occurred.

#define	FDC_COMM_ERR 1
	Communication error on I2C bus.

#define	FDC_DEV_NOT_FOUND 2
	Device not found on I2C bus.

#define	FDC_CONF_ERR 3
	Channel configuration error.

#define	FDC_MEAS_NOT_DONE 4
	Measurement not completed error.

#define	FDC_100_Hz 1
	100 Samples/second sample rate.

#define	FDC_200_Hz 2
	200 Samples/second sample rate.

#define	FDC_400_Hz 3
	400 Samples/second sample rate.

#define	FDC_CH_1 0
	FDC Capacitance channel 1.

#define	FDC_CH_2 1
	FDC Capacitance channel 2.

#define	FDC_CH_3 2
	FDC Capacitance channel 3.

#define	FDC_CH_4 3
	FDC Capacitance channel 4.

#define	FDC_IN_1 0
	Capacitance channel 1.

#define	FDC_IN_2 1
	Capacitance channel 2.

#define	FDC_IN_3 2
	Capacitance channel 3.

#define	FDC_IN_4 3
	Capacitance channel 4.

#define	FDC_CAPDAC 4
	CAPDAC input.

#define	FDC_DISABLED 7
	Channel disabled - GND.

#define	FDC_RP_CH_1 0x80
	Repeat measurement for channel 1.

#define	FDC_RP_CH_2 0x40
	Repeat measurement for channel 2.

#define	FDC_RP_CH_3 0x20
	Repeat measurement for channel 3.

#define	FDC_RP_CH_4 0x10
	Repeat measurement for channel 4.

Detailed Description

Register map for the FDC1004Q component.

Author: Davide Marzorati

Definition in file FDC1004Q_Defs.h.

Macro Definition Documentation

#define FDC1004Q_CONF_MEAS1 0x08

Measurement 1 Configuration Register.

This register allows to configure the measurement for channel 1. A detailed description of the register is reported in Table Meas 1 Conf.

MEAS1 Configuration Register
Field Name	Bits	Description
CHA	[15:13]	Positive input	b000	CIN1
			b001	CIN2
			b010	CIN3
			b011	CIN4
CHB	[12:10]	Negative input	b000	CIN1
			b001	CIN2
			b010	CIN3
			b011	CIN4
			b100	CAPDAC
			b111	DISABLED
CAPDAC	[9:5]	Negative input	b00000	0pF (Minimum Offset)
			...	Coffset = CAPDAC * 3.125 pF
			b11111	96.875 pF (Maximum Offset)
RESERVED	[4:0]	Reserved		Always read 0

Definition at line 157 of file FDC1004Q_Defs.h.

#define FDC1004Q_CONF_MEAS2 0x09

Measurement 2 Configuration Register.

This register allows to configure the measurement for channel 2. A detailed description of the register is reported in Table Meas 1 Conf.

Definition at line 166 of file FDC1004Q_Defs.h.

#define FDC1004Q_CONF_MEAS3 0x0A

Measurement 3 Configuration Register.

This register allows to configure the measurement for channel 3. A detailed description of the register is reported in Table Meas 1 Conf.

Definition at line 175 of file FDC1004Q_Defs.h.

#define FDC1004Q_CONF_MEAS4 0x0B

Measurement 4 Configuration Register.

This register allows to configure the measurement for channel 4. A detailed description of the register is reported in Table Meas 1 Conf.

Definition at line 184 of file FDC1004Q_Defs.h.

#define FDC1004Q_DEVICE_ID 0xFF

ID of FDC1004Q device Register.

This register contains a factory-programmable identification value that identifies this device as a FDC1004Q. This register distinguishes this device from other devices that are on the same I2C bus. The Device ID for the FDC1004Q is 0x1004.

Definition at line 349 of file FDC1004Q_Defs.h.

#define FDC1004Q_FDC_CONF 0x0C

Capacitance to Digital Configuration Register.

This register configures the sample rate of the measurements, thre repeated measurements and the enable of single channels. A detailed description of this register is reported in Table FDC Configuration Register.

FDC Configuration Register
Field Name	Bits	Description
RST	[15]	Reset	0	Normal Operation
RST	[15]	Reset	1	Initiate reset
RESERVED	[14:12]	Reserved		0 (read only)
RATE	[11:10]	Measurement Rate	b00	Reserved
			b01	100 Hz
			b10	200 Hz
			b11	400 Hz
RESERVED	[9]	Reserved		Always read 0
REPEAT	[8]	Repeat Measurements	0	Repeat Disabled
REPEAT	[8]	Repeat Measurements	1	Repeat Enabled, measurements repeated
MEAS_1	[7]	Initiate Measurement	0	Measurement 1 Disabled
MEAS_1	[7]	Initiate Measurement	1	Measurement 1 Enabled
MEAS_2	[6]	Initiate Measurement	0	Measurement 2 Disabled
MEAS_2	[6]	Initiate Measurement	1	Measurement 2 Enabled
MEAS_3	[5]	Initiate Measurement	0	Measurement 3 Disabled
MEAS_3	[5]	Initiate Measurement	1	Measurement 3 Enabled
MEAS_4	[4]	Initiate Measurement	0	Measurement 4 Disabled
MEAS_4	[4]	Initiate Measurement	1	Measurement 4 Enabled
DONE_1	[3]	Measurement Done	0	Measurement 1 Not Completed
DONE_1	[3]	Measurement Done	1	Measurement 1 Completed
DONE_2	[2]	Measurement Done	0	Measurement 2 Not Completed
DONE_2	[2]	Measurement Done	1	Measurement 3 Completed
DONE_3	[3]	Measurement Done	0	Measurement 3 Not Completed
DONE_3	[3]	Measurement Done	1	Measurement 3 Completed
DONE_4	[2]	Measurement Done	0	Measurement 4 Not Completed
DONE_4	[2]	Measurement Done	1	Measurement 4 Completed

Definition at line 227 of file FDC1004Q_Defs.h.

#define FDC1004Q_GAIN_CAL_CIN1 0x11

CIN1 Gain Calibration Register.

The Gain calibration registers contain a gain factor correction in the range of 0 to 4 that can be applied to each channel in order to remove gain mismatch due to the external circuitry. This 16-bit register is formatted as a fixed point number, where the 2 MSBs of the GAIN_CALn register correspond to an integer portion of the gain correction, and the remaining 14 bits represent the fractional portion of the gain correction. The result of the conversion represents a number without dimensions. The Gain can be set according to the following formula: $Gain = GAIN_CAL[15:0]/2^{14}$

The registers are structured as follows:

FDC Gain Calibration Register
Field Name	Bits	Description
GAIN_CALn	[15:14]	Integer part	Integer portion of the Gain Calibration of Channel CINn
GAIN_CALn	[13:0]	Decimal part	Decimal portion of the Gain Calibration of Channel CINn

Definition at line 303 of file FDC1004Q_Defs.h.

#define FDC1004Q_GAIN_CAL_CIN2 0x12

CIN2 Gain Calibration Register.

For a detailed explanation of this register, please refer to FDC1004Q_GAIN_CAL_CIN1.

Definition at line 311 of file FDC1004Q_Defs.h.

#define FDC1004Q_GAIN_CAL_CIN3 0x13

CIN3 Gain Calibration Register.

For a detailed explanation of this register, please refer to FDC1004Q_GAIN_CAL_CIN1.

Definition at line 319 of file FDC1004Q_Defs.h.

#define FDC1004Q_GAIN_CAL_CIN4 0x14

CIN4 Gain Calibration Register.

For a detailed explanation of this register, please refer to FDC1004Q_GAIN_CAL_CIN1.

Definition at line 327 of file FDC1004Q_Defs.h.

#define FDC1004Q_MANUFACTURER_ID 0xFE

ID of Texas Instruments Register.

This register contains a factory-programmable identification value that identifies this device as being manufactured by Texas Instruments. This register distinguishes this device from other devices that are on the same I2C bus. The manufacturer ID reads 0x5449.

Definition at line 339 of file FDC1004Q_Defs.h.

#define FDC1004Q_MEAS1_LSB 0x01

LSB Portion of Measurement 1 Register.

This is the register containing the LSB portion of channel 1 measurement. For additional information on the measurement registers, please refer to FDC1004Q_MEAS1_MSB.

Definition at line 46 of file FDC1004Q_Defs.h.

#define FDC1004Q_MEAS1_MSB 0x00

MSB Portion of Measurement 1 Register.

This is the register cotaining the MSB portion of channel 1 measurement. The capacitance measurement registers are 24-bit result registers in binary format (the 8 LSBs D[7:0] are always 0x00). The result of the acquisition is always a 24 bit value, while the accuracy is related to the selected conversion time. The data is encoded in a Two’s complement format. The result of the measurement can be calculated by the following formula:

Capacitance (pf) = ((Two's Complement (measurement $ [23:0]$ )) / $2^{19})$ + $C_{offset}$

where $C_{offset}$ is based on the CAPDAC setting.

Definition at line 37 of file FDC1004Q_Defs.h.

#define FDC1004Q_MEAS2_LSB 0x03

LSB Portion of Measurement 2 Register.

This is the register containing the LSB portion of channel 2 measurement. For additional information on the measurement registers, please refer to FDC1004Q_MEAS2_MSB.

Definition at line 74 of file FDC1004Q_Defs.h.

#define FDC1004Q_MEAS2_MSB 0x02

MSB Portion of Measurement 2 Register.

This is the register cotaining the MSB portion of channel 2 measurement. The capacitance measurement registers are 24-bit result registers in binary format (the 8 LSBs D[7:0] are always 0x00). The result of the acquisition is always a 24 bit value, while the accuracy is related to the selected conversion time. The data is encoded in a Two’s complement format. The result of the measurement can be calculated by the following formula:

Capacitance (pf) = ((Two's Complement (measurement $ [23:0]$ )) / $2^{19})$ + $C_{offset}$

where $C_{offset}$ is based on the CAPDAC setting.

Definition at line 65 of file FDC1004Q_Defs.h.

#define FDC1004Q_MEAS3_LSB 0x05

LSB Portion of Measurement 3 Register.

This is the register containing the LSB portion of channel 3 measurement. For additional information on the measurement registers, please refer to FDC1004Q_MEAS3_MSB.

Definition at line 102 of file FDC1004Q_Defs.h.

#define FDC1004Q_MEAS3_MSB 0x04

MSB Portion of Measurement 3 Register.

This is the register cotaining the MSB portion of channel 3 measurement. The capacitance measurement registers are 24-bit result registers in binary format (the 8 LSBs D[7:0] are always 0x00). The result of the acquisition is always a 24 bit value, while the accuracy is related to the selected conversion time. The data is encoded in a Two’s complement format. The result of the measurement can be calculated by the following formula:

Capacitance (pf) = ((Two's Complement (measurement $ [23:0]$ )) / $2^{19})$ + $C_{offset}$

where $C_{offset}$ is based on the CAPDAC setting.

Definition at line 93 of file FDC1004Q_Defs.h.

#define FDC1004Q_MEAS4_LSB 0x07

LSB Portion of Measurement 4 Register.

This is the register containing the LSB portion of channel 4 measurement. For additional information on the measurement registers, please refer to FDC1004Q_MEAS4_MSB.

Definition at line 131 of file FDC1004Q_Defs.h.

#define FDC1004Q_MEAS4_MSB 0x06

MSB Portion of Measurement 4 Register.

This is the register cotaining the MSB portion of channel 4 measurement. The capacitance measurement registers are 24-bit result registers in binary format (the 8 LSBs D[7:0] are always 0x00). The result of the acquisition is always a 24 bit value, while the accuracy is related to the selected conversion time. The data is encoded in a Two’s complement format. The result of the measurement can be calculated by the following formula:

Capacitance (pf) = ((Two's Complement (measurement $ [23:0]$ )) / $2^{19})$ + $C_{offset}$

where $C_{offset}$ is based on the CAPDAC setting.

Definition at line 121 of file FDC1004Q_Defs.h.

#define FDC1004Q_OFFSET_CAL_CIN1 0x0D

CIN1 Offset Calibration Register.

The offset calibration registers configure a digitized capacitance value in the range of -16 pF to 16 pF (max residual offset 250 aF) that can be added to each channel in order to remove parasitic capacitance due to external circuitry. In addition to the offset calibration capacitance which is a fine-tune offset capacitance, it is possible to support a larger offset by using the CAPDAC (for up to 100 pF). These 16-bit registers are formatted as a fixed point number, where the first 5 bits represents the integer portion of the capacitance in Two’s complement format, and the remaining 11 bits represent the fractional portion of the capacitance.

The detailed structure of the register is reported in Table Offset Calibration Register.

FDC Offset Calibration Register
Field Name	Bits	Description
OFFSET_CALn	[15:11]	Integer part	Integer portion of the Offset Calibration of Channel CINn
OFFSET_CALn	[10:0]	Decimal part	Decimal portion of the Offset Calibration of Channel CINn

Definition at line 254 of file FDC1004Q_Defs.h.

#define FDC1004Q_OFFSET_CAL_CIN2 0x0E

CIN2 Offset Calibration Register.

For a detailed explanation of this register, please refer to FDC1004Q_OFFSET_CAL_CIN1.

Definition at line 262 of file FDC1004Q_Defs.h.

#define FDC1004Q_OFFSET_CAL_CIN3 0x0F

CIN3 Offset Calibration Register.

For a detailed explanation of this register, please refer to FDC1004Q_OFFSET_CAL_CIN1.

Definition at line 270 of file FDC1004Q_Defs.h.

#define FDC1004Q_OFFSET_CAL_CIN4 0x10

CIN4 Offset Calibration Register.

For a detailed explanation of this register, please refer to FDC1004Q_OFFSET_CAL_CIN1.

Definition at line 278 of file FDC1004Q_Defs.h.

Macros

Detailed Description

Macro Definition Documentation